A practical taxonomy for choosing embedded ML frameworks by constraints first: safety, WCET, hardware class, model size, vendor lock-in, and production realities.

Before writing any firmware, you can know whether an ML model will fit on your target hardware. This guide covers the napkin math: counting parameters for Flash, calculating peak activation memory for SRAM, and estimating inference latency from MAC counts. The running example is vibration analysis for drone motor health on a Cortex-M4.

Deploying neural networks on microcontrollers goes beyond just shrinking models. It requires a fundamentally different approach to system design, memory management, and software architecture. This guide maps the terrain: from tensor arenas and static computation graphs, through the interpreter-vs-AOT tradeoff, to matching model architectures with hardware capabilities from Cortex-M0 to dedicated NPUs.